This invention relates to a phase synchronizing circuit which is configured similarly to a phase-locked loop (PLL), and is adapted to replace a PLL in many applications. A phase-locked loop circuit of the prior art is configured generally as shown in FIG. 1 of the drawings. A phase detector 10 provides an output signal indicative of the phase difference between the signal received at input 1 and the signal received from the voltage-controlled oscillator (VCO) 13, and this phase difference signal is filtered by low-pass filter 11, amplified by operational amplifier 12, and then applied to control the VCO. Operation of such circuits is described for example, in F. Gardner, Phaselock Techniques (second edition, 1979), which is hereby incorporated by reference.
However, this known circuit has the defect that, if the input phase (or frequency) undergoes a stepwise change, considerable time may be required until the phaselocked loop resumes tracking of the input signal. This difficulty is particularly acute when the phase change is close to 180.degree.. This difficulty is known to those skilled in the art as the "hang-up effect", and may be found discussed generally in, for example, Gardner, Hang-up In Phase-Lock Loops, 25 IEEE Transactions on Communications 1210 (October 1977), which is hereby incorporated by reference. FIG. 2 of the drawings shows the delay in phase reacquisition, for various values .phi. of the phase error. As may be seen, when the phase error is very close to 180.degree., reacquisition may require a large number of cycles. The hang-up effect is a particularly unfortunate defect of the conventional phaselocked loops in synchronizer applications for digital communications. In such applications, particularly in phase-shift keying(PSK), the data modulation is likely to cause rapid phase shifts of the signal received, including apparent 180.degree. phase shifts. Such apparent phase changes may also be caused by adjacent channel interference, or other defects of the transmission path. However, in many such applications, it is essential that the clock pulses generated within the receiver be in phase with the clock pulses generated at the transmitter (allowing for transmission path delay). Since decoding of the data often requires a clock (or a regenerated digital carrier pulse train) which is in synchrony with the information being received, the delay in phase reacquisition which may be imposed by the hang-up effect (as shown in FIG. 2) when the input signal shows a sudden apparent phase change of 180.degree., is unacceptable.